Split gate non-volatile memory cells having three conductive gates, and arrays of such cells, are known. For example, U.S. Pat. No. 7,315,056 (“the '056 patent”) discloses an array of split gate non-volatile memory cells, and is incorporated herein by reference for all purposes. The memory cell is shown in FIG. 1. Each memory cell 10 includes source and drain regions 14/16 formed in a semiconductor substrate 12, with a channel region 18 there between. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and over a portion of the source region 14. A select (word line) gate 28 has a first portion 28a that is disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion 28b that extends up and over the floating gate 20. A program/erase gate 30 has a first portion disposed over the source region 14 and is laterally adjacent to the floating gate 20, and a second portion 30b that extends up and over the floating gate 20.
The memory cell is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the PE gate 30, which causes electrons on the floating gate 20 to tunnel through the intermediate insulation from the floating gate 20 to the PE gate 30 via Fowler-Nordheim tunneling.
The memory cell is programmed (where electrons are placed on the floating gate) by placing a positive voltage on the select gate 28, and a positive voltage on the source 14 and a positive voltage on the PE gate 30. Electron current will flow from the drain 16 towards the source 14. The electrons will accelerate and become heated when they reach the gap between the select gate 28 and the floating gate 20. Some of the heated electrons will be injected through the gate oxide onto the floating gate 20 due to the attractive electrostatic force from the floating gate 20.
The memory cell is read by placing positive read voltages on the drain 16 and select gate 28 (which turns on the channel region under the select gate). If the floating gate 20 is positively charged (i.e. erased of electrons and positively coupled to the source 14), then the portion of the channel region under the floating gate 20 is turned on as well, and current will flow across the channel region 18, which is sensed as the erased or “1” state. If the floating gate 20 is negatively charged (i.e. programmed with electrons), then the portion of the channel region under the floating gate 20 is mostly or entirely turned off, and current will not flow (or there will be little flow) across the channel region 18, which is sensed as the programmed or “0” state.
Exemplary operating voltages can be:
TABLE 1Select GateDrainPE GateSourceOperation(28)(16)(30)(14)Erase0010-12Volts0Program1-2Volts~1μA4-6Volts6-8VoltsRead1.5-3.3Volts0.5-1.0Volts00
The architecture of the memory array is shown in FIG. 2. The memory cells 10 are arranged in rows and columns. In each column, the memory cells are arranged end to end in mirror fashion, so that they are formed as pairs of memory cells each sharing a common source region 14, and each adjacent set of memory cell pairs sharing a common drain region 16. All the source regions 14 for any given row of memory cells are electrically connected together by a source line 14a. All the drain regions 16 for any given column of memory cells are electrically connected together by a bit line 16a. All the select gates 28 for any given row of memory cells are electrically connected together by a select gate line 28a. All the PE gates 30 for any given row of memory cells are electrically connected together by a PE gate line 30a. Therefore, while the memory cells can be individually programmed and read, memory cell erasure is performed by pairs of rows (each pair of rows of memory cells sharing PE gates 30 are erased together, by the application of a high voltage on the PE gate line 30a). If a particular memory cell is to be erased, all the memory cells in the two rows are also erased.
Recently, new applications for split gate non-volatile memory cells have been developed that require true single bit operation (i.e. each memory cell can be individually programmed, read, and erased, without any interference from or disturbing the programming state of adjacent memory cells). Therefore, there is a need for an array of split gate non-volatile memory cells having three conductive gates which can be independently programmed, read and erased.